Integrated circuits find application in many of today's consumer electronics, such as cell phones, video cameras, portable music players, printers, computers, etc. Integrated circuits may include a combination of active devices, passive devices and their interconnections. These integrated circuits are commonly formed by imaging multiple reticles and/or mask patterns on a wafer via a process called photolithography.
Generally, the photolithography process and its corresponding equipment consist of a light source transmitted through an optical system onto a reticle or mask with a pattern. The reticle or mask pattern produced by the light is then reduced (typically by a factor of 4 or 5) and aligned to a wafer covered with a light-sensitive photoresist, wherein the desired integrated circuit pattern is then transferred to the photoresist and subsequently to underlying layers. Unfortunately, these integrated circuit patterns tend to vary in density over the topography of a wafer, consequently leading to loading effects during etching and unwanted dishing during a chemical mechanical planarization (CMP) process.
Commonly, dummy fill patterns are generated on wafers to help reduce the density variations across the topography of a wafer. For a dummy fill pattern formed by a multiple exposure method, the dummy fill pattern will either be generated on a single mask with a large blocking layer on the other mask or by using dummy patterns on both masks. Unfortunately, the allocation of a dummy pattern on a single mask with a large blocking layer employed on the other mask will cause the mask transmission intensity to be different for each mask. This unequal mask pattern density distribution will result in different exposure doses and a different contribution to the final photoresist critical dimension (CD) by each mask, thereby affecting the desired density of the dummy fill pattern formed on the wafer. Additionally, the mask pattern density may also affect the mask writing process registration, which can cause a significant mask registration difference between each mask.
On the other hand, the allocation of a dummy pattern between two or more masks can make the process sensitive to alignment offset, thereby distorting the desired shape and affecting the desired density of the dummy fill pattern formed on the wafer. For example, alignment offset in both the X and Y directions between the first and second masks can produce a feature size that is either smaller or larger than desired, depending on whether the data polarity of the mask is clear or dark. Accordingly, the allocation of a dummy pattern between two or more masks can lead to significant variations in CD uniformity and pattern density, thereby adversely impacting the etch rate for an etch process and polish rate for a CMP process.
Thus, a need still remains for a reliable integrated circuit system and method of fabrication, wherein the integrated circuit system includes a uniform density dummy pattern formed by a multiple exposure process that helps to prevent loading and dishing. In view of the ever-increasing commercial competitive pressures, increasing consumer expectations, and diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Moreover, the ever-increasing need to save costs, improve efficiencies, and meet such competitive pressures adds even greater urgency to the critical necessity that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.